1. Field of the Invention
The present invention relates to degeneration techniques for designing memory devices, and in particular to a method, computer readable medium and system for producing an instance of a memory device from a banked memory architecture using a degeneration technique.
2. Description of the Prior Art
There is a continuing trend for the storage requirements of memory devices to increase, as a result of which the size and complexity of those memory devices also tends to increase. However, the larger the memory device, the more power is likely to be consumed accessing it, and the slower the access is likely to be. In order to seek to improve the speed of access and reduce the power consumption, it is known to produce banked memory designs, where the memory device is arranged as a plurality of banks. As a result, accesses can be made to the individual banks, rather than to the memory device as a whole, thereby improving the speed of access and reducing the power consumption.
When designing banked memory devices, there are two general approaches that can be taken. In accordance with a first approach, the memory device can be custom designed for a particular implementation, which can lead to an efficient design. However, the disadvantage of such an approach is that there is little chance of re-using that design in different implementations and accordingly such an approach is costly. In accordance with an alternative approach, a banked memory architecture is developed, and then a memory compiler tool is used to create an instance (i.e. a particular instantiation) of that banked memory architecture to form the design of a required memory device having regard to some required properties of that memory device.
In producing an instance of a memory device from a specified banked memory architecture, the compiler tool may perform a degeneration process in which the rows in each bank can be degenerated in order to produce instances of the memory device containing less rows than the maximum possible. One such known degeneration process is illustrated schematically in FIG. 1. In accordance with the banked memory architecture illustrating in FIG. 1, four banks are provided, each pair of banks sharing peripheral logic 50, such peripheral logic consisting of column decoders, sense amp logic, control circuits, etc as will be understood by those skilled in the art. In accordance with the banked memory architecture to which FIG. 1 applies, it is assumed that the maximum number of rows per memory bank is 64, and accordingly the instance 10 represents the largest memory device that can be produced using the banked memory architecture. As shown in FIG. 1, the instance 10 consists of the four banks 12, 14, 16, 18, each bank containing 64 rows, and each pair of banks sharing peripheral logic 50.
However, the person using the compiler tool may indicate that they require less than that number of rows. Applying the degeneration process, this may result in the production of an instance having less than the maximum number of rows, for example the instance 20 where each of the four banks 22, 24, 26, 28 have 62 rows. However, in accordance with this known degeneration technique, the row degeneration in each bank is constrained to be the same, and accordingly there is no possible instance between the instance 10 and the instance 20. Similarly, the next smaller possibility following the instance 20 is the instance 30 where the four banks 32, 34, 36, 38 each have 60 rows therein. The minimum size possible will be dictated by the minimum allowable number of rows per bank, which may for example be eight rows per bank as shown by the instance 40 of FIG. 1 where each of the banks 42, 44, 46, 48 have eight rows.
Hence, whilst the maximum sized instance will provide 256 rows, the next available instance 20 will provide 248 rows. Accordingly, such an approach leads to a fairly coarse granularity between the available number of rows, as illustrated schematically by FIG. 2 which is a diagram illustrating delay as a function of size. The symbols a, b, c, d in FIG. 2 correspond to the four instances 10, 20, 30, 40 illustrated in FIG. 1. Considering instance 30, this provides 240 rows. If the person using the compiler wants to design a memory device having 240 rows, then instance 30 would be generated. However, if that person wishes to produce a memory device having 242 rows, then in accordance with this degeneration technique the instance 20 needs to be adopted, which as discussed earlier has 248 rows, i.e. six rows which are not necessary for the indicated device. As a result, from FIG. 2 it will be seen that due to the need to produce a memory device according to instance 20, the resultant jump in access delay is relatively coarse, potentially putting pressure on the designer to find a way of removing the need for the two additional rows, i.e. thereby enabling the instance 30 to be adopted.
Coupled with this problem, there is a continuing trend for memory architectures to become more highly banked, i.e. to include more and more banks, and from the above description of FIGS. 1 and 2 it will be appreciated that as more banks are included, the coarseness between the possible instances becomes even greater. Hence, considering the earlier example, the delay penalty resulting from the requirement for the two extra rows becomes even larger.
Additionally, it will be appreciated from FIG. 1 that as the memory device instance decreases in size, the efficiency of the resultant memory device is reduced due to the relative overhead of the peripheral logic 50. In particular, it can be seen that when adopting the instance 10 the peripheral logic 50 is shared between 128 rows, whilst when adopting the instance 40, the peripheral logic 50 is shared between 16 rows. Hence, the area required to produce a memory device according to the instance 40 is less efficient than the area required to produce the instance 10.
Accordingly, it would be desirable to provide an improved technique for producing instances of memory devices from a banked memory architecture.